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AD1

12 A/D Channels (±1.25 to ±10.0 VDC FSR); 24-bit Sigma-Delta

Module AD1 features 12 channels with up to 24-bit Sigma-Delta A/D converters for each individual channel. The maximum programmable, expected full-scale range input for the AD1 module is ±1.25 to ±10 VDC. The A/D converters have programmable sample rates of up to 256 kHz.

The input range and gain is also field-programmable for each channel. The ability to set lower expected, full-scale voltage gain ranges assures the use of the full resolution. Each channel includes a fixed, second order, anti-aliasing filter and a digital post filter with a programmable breakpoint that enables users to field-adjust the filtering for each channel.

The extended A/D FIFO buffering capabilities of these modules supports greater storage/management of the incoming signal samples (data) for post-processing applications. Data samples can be stored in the buffer either at the maximum programmed base A/D sample rate or by an integer-divided sample rate. Programmable FIFO buffer thresholds maximize data flow control (movement in and out of the FIFO). Incremental relative time-stamping between samples also is provided as a programmable option.

All A/D channels are self-aligning and continuous Background Built-in-Test (BIT) status is provided for channel health and operation feedback. On a rotating basis, each channel is automatically trimmed/tested for optimal conversion and reliability to eliminate offset and gain errors throughout the entire operating envelope (temperature and drift control). Open inputs are sensed and flagged.

Features
  • Number of Channels: 12
  • ADC Type / Architecture: Σ-Δ / Individual
  • Key Characteristics Range (max): ±10 V
  • Effective Resolution Bits: 24
  • Sampling Rate (max.): 256 kHz / Channel

Specifications
  • Resolution: 24-bit Sigma-Delta A/D converters. One per channel.
  • Input Format: Differential voltage (may be used as single-ended by grounding one input).
  • Input Scaling: Twelve (12) bipolar or unipolar channels (volts). Programmable, per channel, as Full Scale (FS) range inputs of 10.00, 5.00, 2.50 or 1.25 volts where range is -FS to +FS or 0 to FS VDC. The ability to set lower voltages for FS assures the utilization of the full resolution
  • Overvoltage Protection: No damage up to ±12 V continuous; ±30 V momentary.
  • Open Input Sense: This module will sense and report unconnected inputs.
  • Input Impedance: 20 MΩ (Differential), 10 MΩ (Single -ended)
  • INL (Linearity): ±0.05% FS range over temperature (voltage), to 16-bits
  • Gain Error: ±0.05% FS range
  • Offset Error: ±0.02% FS range
  • Sampling Rate: 256 kHz max. per channel, programmable
  • Data Buffering/Triggering: See Operations Manual for details.
  • Bandwidth: 110 kHz per channel
  • Acquisition/Conversion Time: 4.4 μs at 256 kHz sampling rate. See manual for conversion time at lower sample rates
  • Programmable Filter: Each channel incorporates a fixed second order anti-aliasing filter (110 kHz bandwidth) and a post filter that has a digitally adjustable break point programmable up to 115 kHz.
  • Common Mode Rejection: 70 dB min. at 60 Hz. Roll off to 50 dB min. at 10 kHz.
  • Common Mode Voltage: Signal voltage plus Common mode voltage is 9.5 volts for the lowest range and 11.5V for higher ranges. Note: A/D differential inputs must not “float”. Input source must have return path to ground.
  • Output Logic: Bipolar output in two's complement. Bipolar output range from FF80 0000 max. negative; 007F FFFF is max. positive (FS) Unipolar output range from 0 to 00FF FFFF (FS).
  • ESD Protection: Designed to meet the testing requirements of IEC 801-2 Level 2 (4 KV transient with a peak current of 7.5 A and a Tc of approximately 60 ns)
  • Power: 5 VDC @ 600mA typ, +/-12 VDC @ 310mA (typ.)
  • Ground: Channel inputs are differential, referenced to isolated module AGND, isolated (250 V minimum peak isolation) from system power/ground.
  • Weight: 1.5 oz. (42 g)
  • VREF Detail: VREF output @ 4.096 V (≤ 10 mA)
  • Signal- to- Noise Ratio (SNR): Minimum of 60dB
Block Diagram
Documentation
6/15/2023 11:40:40 AM
5/6/2024 11:04:13 AM
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